EPD Professional Design Suite (EPDP)

The EPD Professional Design Suite created for IC Packaging designers and substrate related PCB, RF, Flex, Schematic, Ceramic, Die Bump, BGA, Lead Frame, Bi-Direction Gerber and GDS, 3D tools, Advanced routing, Documentation tools, Panelizing, ODB, Bondwire Export, IC Packaging Tools for Lead Frame, BGA, Semiconductor Packaging.

Watch a Basic Video Demonstration for building an RF Design

Watch a Basic Video Demonstration for building Hybrid MCM Design

Watch a Basic Video Demonstration for building BGA Design


Dies may be imported from any source, including .txt, .xls, .aif, .die, .dwg, .dxf, bit maps and document scans. It has a process for the semi-automatic creation of QFP and similar type Lead Frames that have Gull Wing style I/O leads and fully parametric design of QFN type Lead Frames.

This software contains the base EPD that is capable of designing and checking complex PCBs. Lead frames are seen as multi-layer PCBs with boundary nets and sloping vias.

Various other tools are available for modification of Lead Frame designs. It captures dies from any source and automatically designs the wire bonding in any Lead Frame type.

Automatic wire bonding design software that can insert single, stacked and side by side die(s) and automatically wire bond them to any Lead Frame blank using complex rules or with predefined net lists. It intelligizes existing Lead Frame blanks or populated Lead Frames from any source for subsequent processing.

The Advanced DRC software verifies all complex lead frame and wire bonding design rules. After wire bonding you can automatically create a full solid model that can be exported as ACIS or STEP for export to thermal analysis tools.

The Lead Frame Library Search software to filter large libraries of EPD-intelligized Lead Frames and provides a search function for best available Lead Frame for a die

The Lead Frame Intelligizer module captures the lead tips as it converts legacy unintelligent drawings into intelligent designs compatible with Cadence’s APD and SIP

Intelligize Existing Designs

Lead Frame Blanks or entire designs including dies and bond wires

Design Lead frames, Place Die(s) in blanks and add bond wires, Stacked Die(s)- even side by side stack ups, New blank designs – Single & MCM.

Semi-Automatically intelligize the unintelligent metal/leadframe artwork and lead tips. And it uses the ATTINTEL command to intelligize any combination of dies and wires including stacked dies and side by side stacks.

This software intelligizes any Lead Frame design so that advanced functions available in EPD may be used including sending into Cadence SIP for co-design. It is a semi-automatic, yet extremely fast process to turn Lead Frame designs that were manually drawn to the standard CDS data format.

LFintel intelligizes the metal/leadframe and AttIntel intelligizes the die and the bond wires. Configuration files made during one intelligization can be saved and re-used to automatically configure similar jobs.

True 3D Modeling

Makes perfect 3D models which can be exported via ACIS or SAT formats to electrical, thermal and mechanical analysis tools.


  • One of the most important features of any Electronic Design Automation (EDA) layout system is its 3D architecture. As designs trend toward increased speeds/densities, miniaturization of packages/modules, and integrated components with System-in-Package (SiP) technology, it is increasingly important to verify the package integrity using a modern, 3D-based system.

  Read More 3D Utility Module included with this Suite

DRC and Connectivity Functions

The NETCHK command provides connection verification and netlist generation. Extract the netlist and optionally compare it to a reference netlist. It reports 28 different error types.

More about Netchecking

Run the ADRC (Advanced Design Rule Checker) command using complex 2D rules and rules with arrays of settings. This tool provides complete DRC and MRC rules to ensure that the lead frame meets all standard and custom design and manufacturing rules before being sent to manufacturing.

More about ADRC

MAKEEDGE is an automatic boundary edge generator that provides graphical data for chemical milling with etch compensation. Boundaries can be automatically generated from the non-boundary geometries or from overlapping boundary geometries.

More about Edge

BGA and IC Packaging

  • Bond-finger / bond-wire fanout uses parametric controls for unlimited creative flexibility

  • Automatic creation of JEDEC or custom BGAs including reading in an MS Excel® file with Netnames and Class names initialized

  • Automatic and interactive Netlist Creation tools for single chips and MCMs

  • Support for all package types including new technologies BGA, MCM, CSP, BUM, WSP, etc.

  • Six ways to read in die information for automatic die creation

    • Reads .LIQ files

    • Reads .DIE files

    • Reads .DWG files

    • Reads GDSII Stream files

    • Digital scans from photographs

    • Manual data entry

  • Automatic power rings with automatic signal name assignment from netlist or from die

  • Automatic Dogbone Array creation with option for a 2 via stair step on each Ball and many angle options

  • See more Info